Advances in semiconductor technology have yielded denser and faster circuits. Operation speed or response time determines the minimum time in which information can be either accessed from the storage locations or information written thereto. There are a number of factors that determine the speed with which information can be accessed in a memory array. These are such things as intermediate latches for column and row addresses, generation of timing signals, buffer delays, etc. Some of these factors are a function of design such as, for example, the sequence of timing signals utilized to access the memory array which require a predetermined number of logical steps before access is allowed. Other factors that affect response time are such things as circuit parasitics.
In accessing a memory array, a column address and a row address are input to the device and normally strobed into column and row latches by a column address strobe (CAS) and a row address strobe (RAS), respectively, RAS and CAS in a typical memory would allow access to one location in the memory. An additional location would require this cycle to be repeated with its inherent delays. There are a number of modes that have heretofore been utilized to increase access time for a particular application. One technique is "paging" and the other technique is "static column decode". In the page mode, a row address is strobed into the row address latch to select a row in the memory array. Thereafter, it is only necessary to generate CAS followed by an address to access a particular column. Sequential CAS signals followed by a different address will allow each column in a particular row to be accessed without requiring the generation of RAS for each memory location accessed in a given row. This eliminates the required delay between the generation of RAS and CAS, thus increasing access speed.
In the static column decode mode, no column address latch is provided. Rather, only a row address latch is provided for latching the row address with the column address being fed directly to the column decoder. After the selection of a given row by latching the row address into the row address latch, it is only necessary to then asynchronously input column addresses. As soon as the column address is input, the column decoder decodes it and activates one of the column lines. Therefore, only the inherent delays of the column decoders and the inherent access time for each of the memory cells determines the delay between generation of the column address and output of valid data. There is no delay incurred as a result of the column address latch or the timing signals required to effectively latch data therein.
The use of page mode requires both a RAS input and a CAS input and an internal latch whereas the static column decode mode requires only a RAS input. The two are therefore not compatible in present circuits. Therefore, a need exists for a memory having an integrated page mode and static column decode mode on the same device without increasing the number of pins over that required for the page mode device.